s1
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Sun Microsystems' OpenSPARC T1 microprocessor (codename Niagara), recently released under the GPL license, features 8 SPARC CPU Cores and several peripherals; the S1 Core takes only one 64-bit SPARC Core from that design and adds a Wishbone bridge, a reset controller and a basic interrupt controller, to make it easy for a system engineer to integrate the design.

Simply RISC S1 Core (codename Sirocco) shares with the SPARC v9 Core, from which it is derived, the ability to execute four concurrent threads at the same time; and Operating Systems that support Sun's microprocessor, such as OpenSolaris and GNU/Linux distributions (like Ubuntu and Gentoo), will then detect four different CPUs even if on the chip the CPU core is only one.

The development environment of the S1 Core can run on any Unix/Linux box and no commercial tools are required, since both simulation and synthesis of the Verilog files of the design can be performed using the free software Icarus Verilog.

Due to its Wishbone-compliant bus interface the S1 Core can be easily interconnected to several cores freely available on OpenCores.org to build up a System-on-a-Chip.

You can use the left menu to access forums, mailing lists and files; currently the design is not under CVS but you can download the full package as a single file.